The present invention relates to fabrication of integrated circuits.
All useful integrated circuits need to have more than one level of conductor. Some sort of interlevel dielectric is therefore necessary to separate these layers from each other, and such interlevel dielectrics are used in a tremendous variety of integrated circuit processes: NMOS, CMOS, I-squared-L, ECL, ALS, high voltage, smart power, memory, logic, analog, gate arrays, and many other families of integrated circuits all have their own particular processing and interconnect demands, but all typically use multiple patterned overlaid layers of thin-film conductors, and all accordingly need to use interlevel dielectrics to separate these conductor layers. The present invention provides an improvement in the conventional processes which is applicable nearly anywhere that interlevel dielectrics are used.
For example, in conventional NMOS technology a polysilicon thin film will be patterned to provide a first level of interconnect (and also transistor gates). A relatively thick layer of a doped silicate glass (such as phosphosilicate glass ("PSG") or borophosphosilicate glass ("BPSG")) will be deposited over this conductor level to provide the first interlevel dielectric. (This layer is also often conventionally referred to as "MLO", or multi-level oxide, although it is not a pure oxide.) Contact holes are patterned in locations which will permit the following metal layer to make electrical connections between transistors in the substrate and/or polysilicon lines. Any implant which is needed for the contact locations (e.g. to assure good ohmic contact) is done at this time, and then the interlevel dielectric is reflowed. "Reflow" means that this glass is heated to a high enough temperature that surface tension effects cause its surface to smooth out. This not only gives the glass a fairly smooth surface, but also causes its sidewalls next to the contact holes to be fairly gently sloped. Similarly, the places where the patterned polysilicon under the glass has vertical edges will not cause as sharp an edge at the upper surface of the glass: where the underlying polysilicon has a sharp edge, the glass will have a smoother slope.
These smoothing effects are highly desirable, because they permit good coverage by the overlying conductor levels. That is, in this conventional process, after the reflow process a metal (such as aluminum) will be deposited (e.g. by sputtering) and then patterned. The etch which patterns the metal layer needs to be anisotropic, to keep good control over the linewidth of this layer; but, when such anisotropic etching is used, problems can occur where the metal runs over an uneven surface. Where the metal lies on a slope (even a very narrow and localized slope), this portion of the metal will take longer to etch away than the metal on flat areas will. The steeper and higher the slope is, the more overetching time will be required; but the underlying structures will not be totally inert to the etch used to cut the metal layer, and too much overetching can damage them. Thus it is desirable not to use more overetch than is necessary to reliably remove all of the unwanted metal; but if the surface under the metal has any local slope which is steeper or higher than anticipated, the amount of overetching may suddenly turn out to be insufficient to remove all of the metal. In this case, portions of metal may remain as narrow lines running along the more steeply sloped portions of the underlying surface; such unwanted lines are known as filaments, and the prevention of filaments is consistently one of the major objectives (and often one of the major problems) in developing a process for patterning conductors, since such filaments can of course short out whatever circuit is sought to be fabricated, or introduce large amounts of unexpected parasitic capacitance, or have other adverse effects on the functionality of the circuit being fabricated.
Thus, control of the surface topography of the interlevel dielectric is critical to control of subsequent processing steps, and particularly to the avoidance of filaments in the patterning of overlying conductors.
A related problem in the prior art of interlevel dielectrics is separation of the dielectric during reflow. That is, where the MLO 10 is deposited over conductor lines 16 which are spaced apart by a certain critical distance, the as-deposited MLO 10 is likely to have a fairly steep valley 13 in its surface between the conductors 16, as shown in FIG. 3A. However, the surface tension effects during reflow may cause the MLO to separate rather than coalesce at the location of this valley 13, so that the pre-reflow valley 13 is converted into a crack 14 which cuts right through the reflowed MLO 12 (as shown in FIG. 3B), which of course can destroy the functionality of the circuit.
Another criterion for interlevel dielectrics is reduction in parasitic capacitance. The capacitance between the two conductor levels which are separated by the interlevel dielectric can be a significant component of the distributed capacitance which increases the RC time constant (and therefore degrades the propagation speed) of the conductor. Such parasitic capacitances may also be pattern-dependent, and can therefore throw a designer's modelling of his circuit completely off.